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Espressif Systems /ESP32-S3-ULP /RTC_I2C /INT_RAW

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Interpret as INT_RAW

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SLAVE_TRAN_COMP_INT_RAW)SLAVE_TRAN_COMP_INT_RAW 0 (ARBITRATION_LOST_INT_RAW)ARBITRATION_LOST_INT_RAW 0 (MASTER_TRAN_COMP_INT_RAW)MASTER_TRAN_COMP_INT_RAW 0 (TRANS_COMPLETE_INT_RAW)TRANS_COMPLETE_INT_RAW 0 (TIME_OUT_INT_RAW)TIME_OUT_INT_RAW 0 (ACK_ERR_INT_RAW)ACK_ERR_INT_RAW 0 (RX_DATA_INT_RAW)RX_DATA_INT_RAW 0 (TX_DATA_INT_RAW)TX_DATA_INT_RAW 0 (DETECT_START_INT_RAW)DETECT_START_INT_RAW

Description

interrupt raw register

Fields

SLAVE_TRAN_COMP_INT_RAW

slave transit complete interrupt raw
ARBITRATION_LOST_INT_RAW

arbitration lost interrupt raw
MASTER_TRAN_COMP_INT_RAW

master transit complete interrupt raw
TRANS_COMPLETE_INT_RAW

transit complete interrupt raw
TIME_OUT_INT_RAW

time out interrupt raw
ACK_ERR_INT_RAW

ack error interrupt raw
RX_DATA_INT_RAW

receive data interrupt raw
TX_DATA_INT_RAW

transit data interrupt raw
DETECT_START_INT_RAW

detect start interrupt raw

Links

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Register License

Copyright 2023 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data